Pulse position error detector



Oct. 17, 1961 T. E. LENIGAN PULSE POSITION ERROR DETECTOR 2 Sheets-Sheet1 Filed Aug. .'51, 1960 Thomas E Lenigan, INVENTOR A TToR Y s.

Oct. 17, 1961 T. E. LENIGAN y 3,005,165

PULSE PosmoN ERRoR DETECTOR Filed Aug. 31, 1960 2 Sheets-Sheet 2 TRIGGERE/Mj 1ER l 3e I l0,000yds. GlpSECS o l TTHREsHoLD Thomas E.Lenigan,/THRESHOLD INVENTQR,

BY M si PULSE POSITIN ERROR DETECTGR fr' This invention relates to pulsegenerating systems and particularly to a method and means ofsynchronizing two such systems.

There is a need in some pulse positioning applications for a means ofautomatically placing a pulse whose position is variable'with time intocoincidence with a second pulse whose position is also variable withrespect to time. As an example, we may have two radar Vrange units eachof which measures distance to a target in terms of elapsed time betweenan initial pulse representing the instant of transmission of a signalfrom the radar transmitter and a second pulse which is placed incoincidence with the returned signal from the target. ln transferringtarget information from one radar to the other, the range gating pulseof the second radar, which may be occurring either earlier or later,must be positionedtorthcasame target that I has been selected by thefirst range unit.

In the past, this has been accomplished by deriving an on-ot errorvoltage of a polarity determined by the relative time position of thetwo pulses such as to drive the tracking range unit pulse toward theacquisition range pulse. On arriving at this position the track rangeunit will oseillate about the correct position. The operator then has totake control and manually position the tracking unit. The method hasmany disadvantages, particularly it may not be used when the radars areremote from one another.

It is an object of the present invention to provide an all electronicmeans for indicating the sense and magnitude of the pulse separation oftwo systems which may be readily employed to control one of the systemsto obtainr synchronization with the other.

To examine the invention basically, assume that there exists two delaytype pulse generating systems which are synchronously triggered by anexternally produced reference pulse. Each of these systems then emit adelayed pulse at some determinable time after the reference triggerpulse. Finally, assume that with respect to at least one of the systems,say a iirst' of the systems, the period of delay is variable andresponsive to an electrical signal, one polarity of signal causing thedelay to increase and the other causing it to decrease. Given theproblem of synchronizing the delayed pulses of the first generatingsystem With the delayed pulses of the other, second, generating systemthe present invention contributes a pulse position error detector(difference in pulse position) which supplies the requisite signal tovary the time position of the delayed pulses of the iirst system toproduce the desired alignment. f

ln accordance with the invention means are provided to develop a pulse aof a duration equal to the interval between a delayed pulse of a firstgenerating system and the nent occurring trigger pulse, and a pulse b ofa duration equal to the interval between the delayed pulse of a secondgenerating system and the next occurring trigger pulse. A firstcoincidence circuit is arranged to provide an output responsive to ythecoincidence of the delayed pulse or function thereof, of the firstgenerating system and pulse b; and a second coincidence circuit'isarranged to provide an output responsive to the delayed pulse, orfunction thereof, of the second generating system and pulse a. Theoutputs of the coincidence circuits are integrated and differentiallycombined to provide a D.C. error voltage which will provide a controlsignal which will drive one of the generating systems to causecoincidence in the delayed pulses.

' The objects and*features pfetlaeeirufen-tien--willY became moreapparent by reference to the following description and drawings inwhich: Y

FIGURE l is a block diagram of an embodiment. of the invention;

FIGURE 2 is a schematic circuit diagram of an embodiment of theinvention; `FIGURES 3 and 4 show Various graphs illustrating theoperation of the invention.

Referring now to FIGURE l, there is shown delay type pulse generators Aand B which are driven with a trigger or reference pulse and whichinclude means for producing a pulse at some point in time betweenreference pulses. Pulse generator A provides variable delay means suchas 'an Yeiect'ric'aiiy driven?adj'establephase shifter responsive to avoltage, forY adjusting this time of occurrence. The output of generatorA is fed to an input of bistable multivibrator or ip-ilop 1li and theoutputof generator B is fed to an input of ip-ilop 12. The reference ortrigger pulse is also applied to an input of each flip-flop to produce aconduction state in each of the flip-flops opposite to that produced byan output of one of the generators. The output of vdip-tldp'1li isednthrough circuit 13 to coincidence detector 14 andJ throughdiierentiating circuit 16, to coincidence detector 18. The output ofliip-liop 12 is fed through integrating circuit 15 to coincidencedetector 1S and through differentiating circuit Z0 to coincidencedetector 14. The output of coincidence detector 14 is integrated bycapacitor 22 and applied to one input of diiferential cathode followerampliiier 24 and the output of coincidence detector 13 is integrated bycapacitor 26 and fed to the other input of differential ampliiier 24.The differential output of amplifier 24 indicates the sense and isproportional to the magnitude of the time difference betweenthe outputof pulse generator A and pulse generator B. This out- Vput is fed to acontrol input of generator A to appropriately cause the output ofgenerator A to advance or retard to produce coincidence with the outputof generator B.

To further examine the operation of the circuit of FIG- URE l, referenceis made to FIGURE' 3. FIGURE 3a illustrates the occurrence of thetrigger pulse and the output pulses a and b of generators A and B,respectively. Assume as shown, neither generator A nor B is beingcontrolled by the output of dilerential amplifier 24 and a and b occurindependently. Pulse a is applied to flip-flop 10 and the rectangularWave shown` in FIG- URE 3b occurs, pulse a causing the rise portion ofthe waveform and the trigger pulse causing the fall portion, asindicated by the time coincidence with FIGURE 3a. In a similar mannerpulse b and the trigger pulse applied to dip-flop 12 produce at theoutput of ip-op 12 the rectangular waveform shown in FIGUREc.` An outputof iiip-llop 10 is partially integrated by integrator 13 to provide agradual rise, one with a decreasing slope, to the leading edge. Thismodified Waveform, shown in FIGURE 3d, is applied -to an input ofcoincidencel dei tector 14. Similarly an output of hip-flop 12 ispartially integrated by integrator 15 to provide a gradual rise with adecreasing slope. This modied' Waveform, shown in FIGURE 3e, is appliedto an input of coincidence circuit 18. An output of ip-flop 10, asdifferentiated in diiierentiator 16 and illustrated in FIGURE 3f, isapplied to an input of coincidence detector 18. Similarly an out.-

put of ilip-iiop 12, as diierentiated in dierentiator 20 Y andillustrated in FIGURE 3g, is applied to coincidence circuit 14. FIGURE3h illustrates by a dashed line the threshold of response of coincidencedetector 14 and the. combined inputs by solid lines.

As shown, detector `11i will provide an output to storage capacitor 22kcorrespondking to the dierentiated pulse input to detector 14. The

solid line in FIGURE 3i illustratesthe combined inputs to detector I8.In this instance, however, as there is no coincidence, there is nosignal above the dashed line threshold and no output is furnished bydetector 18 to capacitor 26. Accordingly differential amplier 24'k willprovide an output of a polarity coded to the particular plotting atypical outputofamplitier 24 vs. pulse separan n tion, with theseparation, lead or lag, illustrated in both time and equivalent radarrange. Due to the slope of the integrated inputs tok coincidencedetectors 14 and 18 (shown in FIGURES 3d and 3e), the error voltageoutput of differential amplifier 24 decreases as the pulses approachcoincidence kand is zeroV when coincidence is reached.

FIGURE 2 shows a schematic circuit diagram which` generally follows theblock diagram in FIGURE l. Flipiiop 10 consists of two triode amplifiers30 and 32, direct current coupled from plate to grid through resistor 34and 36 paralleled by capacitors 38 and 4i? and khavinga common cathoderesistor 42. Anode power is applied to triode 30 through resistor 42 andto triode 32 through series resistors 44 and 46. Positive referencektrigger pulses are applied through capacitor 48 across resistor Sil tothe grid input of triode 32. Positive a pulses from generator A areappliedk through diode 54 across resisn tor 56, through capacitor 5S,across resistor 6d to the grid d input of triode 3i). The flip-flopoutput is taken from triode 32 from the interconnection of anoderesistors fifik and 46. This output, fed through coupling capacitor 62,is first clamped to a positive going maximum of ground potential bydiode 64. It is then fed across resistor 65 to the grid input of triode63 of coincidence detector 14 through resistor 66 and across capacitor68. The R-C circuit of resistor 66 and capacitor 68 contribute theintegrative eifect causing the gradual rise of the leading edge of thewaveform shown in FIGURE 3d. VDiode 67 bridges resistor 66 and is poledto short resistor 66 during the period corresponding to the trailingedge of FIG- URE 3d and `thus provide the sharp drop indicated. A secondoutput from capacitor 62 is differentiated by the combination ofcapacitor 70 and resistor 72. Only the dierentiated leading, positive,edge of the differentiated Waveform is retained, negative overshootbeing bypassed by diode 74. The resulting differentiated pulse shown inFIGURE 3f, is applied to the grid of triode inverter amplitier 76through resistor 78. This inverter amplifier includes triode 80, anoderesistor 82 and cathode resistor 84 bypassed by capacitor 86. Thenegative pulse output of inverter 76 is fed through capacitor S3 acrossVresistor 90a to the cathode of triode 63a of coincidence detector 18.

Elements in nip-flop 12, coincidence circuit 1S, inverter 77 Vandrectifier circuit 93 bear the Vsuffix a added to their counterpartreference numerals in flip-flop 10, coincidence circuit V14, invertercircuit 76 and rectifier 91 and function in the same manner. Due'howeverto the initial difference in time position of the input pulse b (FIGURE3a) to flip-flop 12, (compared with the position of pulse a applied toflip-flop 10), the leading edge of the output of nip-flop 1-2 (FIGURE3c) which is triggered by pulse b is delayed with respect to the outputof liip-iiop 10 (FIGURE 3b). Y

In operation triode 63 of coincidence `circuit 14 conducts when thenegative output of inverter 77 applied to the cathode of triode 63 whenadded to the voltage impressed on the grid of triode 63 from flip-nop 10is sulcient to exceed threshold bias. This is illustrated in FIGURESh,where the negative cathode pulse is represented as a positive grid pulseand the net grid voltage rises to exceed threshold. As shown, triode 63will conduct a maximum amount during the period of the cathode pulsesince the flat portion of the other input is adjusted to a thresholdvalue and the cathode pulse is coincident with a flat portion. At thesame time triode 63a will not conduct since there is no suchcoincidence. This is shown in FIGURE 3i.

Output pulses appearing across the output load resistor 92 for triode 63are fed to rectifier circuit 91 kthrough capacitor 94, resistor 96across resistor 97`and connection of the ungrounded terminal of'capacitor 22 to the grid of triode ofarnpliier 24 and the ungroundedterminal of capacitor 26 to the grid of triode :1. kThe output ofamplifier 24 appears across the ends of potentiometer 167 which areconnected to the cathodes of triodes 105 and IIilSa. The center, ormovable contact of potentiometer `M7, is connected to the negativeterminal of power source 109 through resistor 1310. The exact point ofcoincidence, for zero output may be adjusted by adjusting the positionof the movable contact of potentiometer 107. The output of amplifier 24is fed back to generator A to control the pulse position of the outputof generator A to achieve coincidence with the pulse output of generatorB kpreviously described.

While the foregoing is a description of the preferred embodiment, thefollowing claims are intended to include those modifications andvariations that are within the spirit and scope of my invention.

The following invention is claimed:

1. A pulse synchronization circuit for indicating the error insynchronization of iirst and second pulses, said pulses being producedin response to a trigger pulse and which pulses are delayed with respectto the trigger pulse, said circuit comprising first pulse forming meansresponsive to said rst pulses and artrigger pulse for producing lapulse, the leading edge of which is coincident with the occurrence of apulse output of the first pulse generating source and the trailing edgeof which is coincident With said trigger pulse, second pulse formingmeans responsive to said pulses and said trigger pulse for producing apulse, the leading edge of which is coincident with the occurrence of apulse output of said second pulse generating source and the trailingedge of which is coincident with said trigger pulse, first integratingmeans responsive to a pulse output of said first pulse forming means forshaping the leading edge of said last named output to provide agradually decreasing slope, second integrating means responsive to apulse output of said second pulse forming means for shaping the leadingedge of said last named pulse output to provide a gradually decreasingslope, first differentiating means responsive to the pulse output ofsaid first pulse producing means for differentiating the leading edge ofsaid last named pulse output, second differentiating means responsive tothe pulse output of said second pulse producing means fordifferentiating the leading edge of said last named pulse output,` firstcoincidence means responsive to the output of Ifirst integrating meansand said second differentiating means for providing a first output whenboth inputs are present, second coincidence means responsive to saidsecond integrating means and said rst diierentiating means for providinga second output when both inputs are present, third integrating meansresponsive to said first output for deriving a potential which is afunction of the average value of said first output, fourth integratingmeans responsive to said second output for deriving a potential which isa function of the average value of said second output, dierential meansresponsive to said third and fourth integrating means outputs forsubtracting said outputs.

2. The circuit set forth in claim l further comprising a pulse systemcomprising trigger pulse means for providing said trigger pulses, rstand second said generating means Vcomprising means for providing saidfirst andV No references cited.

